Recently, the speed of integrated circuit memory devices, for example, dynamic random access memories (DRAMs), has increased to improve the performance of existing systems. However, increasing demand for improved systems may require DRAMs that can process even more data at even higher speeds. Accordingly, synchronous dynamic random access memories (SDRAMs) that operate in synchronization with system clocks have been developed for high-speed operation, thus significantly increasing data transmission speeds.
There are limitations on the amount of data that may be input to and/or output from a memory device per cycle of a system clock. To address these limitations, dual data rate (DDR) SDRAMs have been recently developed in order to further increase the transmission speed of data. DDR SDRAMS input and/or output data in synchronization on both the rising edge and the falling edge of a clock.
Reliable data transmission may be possible when the duty cycle of a clock signal is equivalent to 50% (a 50/50 duty cycle) in an integrated circuit memory device, for example, a DDR SDRAM or a direct rambus dynamic random access memory (RDRAM). Thus, when a clock signal having a duty cycle that is greater than or less than 50% is provided as an input, the device may not perform very well. Duty cycle correction circuits have been developed to address this problem.
As stated, for reliable operation internal clocks used in integrated circuit memory devices are preferably symmetric, i.e., have a duty cycle of about 50%. However, external clocks input into integrated circuit memory devices are typically asymmetric, i.e., the duty cycle is not 50% and may be further distorted by characteristics of the integrated circuit memory device. Duty cycle correction circuits receive external clock signals and generate internal clock signals having duty cycles of about 50%.
Conventional duty cycle correction circuits may be analog or digital. Referring now to FIG. 1, a block diagram illustrating conventional analog duty cycle correction circuits will be discussed. As illustrated in FIG. 1, the analog duty cycle correction circuit 100 includes a duty cycle detector circuit 104 and a duty cycle corrector circuit 102. The duty cycle detector circuit 104 may generate different output voltages based upon the duty cycle(s) of the input clock signal(s). The duty cycle corrector circuit 102 may be configured to receive first and second external clock signals ECLK and ECLKB and generate first and second input clock signals having a duty cycle of about 50% based on the voltages generated by the duty cycle detector circuit 104, i.e., to correct the duty cycle of the clock of the clocks using the voltages dcc and dccb provided by the duty cycle detector circuit 104.
The duty cycle detector circuit 104 may include a charge pump 103 as, for example, illustrated in FIG. 2. Referring now to FIG. 2, the charge pump 103 is configured to charge a capacitor C21 when the clock signal CLK is at a logic high level and discharge the capacitor C21 when the clock CLK is at a logic low level. The duty cycle detector circuit 104 may also be configured to output an average charge value voltage Vcp indicating the charge stored in the capacitor C21. Typically, the duty cycle detector circuit 104 includes first and second charge pumps coupled to first and second input clock signal lines. Thus, the duty cycle detector circuit 104 may output first and second average charge values dcc and dccb (FIG. 1) corresponding to the internal clock signal ICLK and complementary internal clock signal ICLKB, respectively.
Referring now to FIG. 3, a graph illustrating outputs of the duty cycle detector circuit 104 as a time function (seconds) with respect to voltage (V) will be discussed. As illustrated in FIG. 3, when power is supplied to the integrated circuit device, the duty cycle detector circuit 104 outputs first and second average charge values dcc and dccb corresponding to the first and second charge pumps, respectively, of the duty cycle detector circuit 104. The first and second average charge values dcc and dccb correspond to the first and second internal clock signals ICLK and ICLKB. The difference 302 between the first and second average charge values dcc and dccb increases as the difference between the duty cycles of the first and second input clock signals increases. When the first and second input clock signals ICLK and ICLKB have a duty cycle of 50%, the average charge values dcc and dccb are typically the same.
Referring now to FIG. 4, a schematic circuit diagram illustrating a duty cycle corrector circuit 102 used in conventional duty cycle correction circuits will be discussed. As illustrated in FIG. 4, the duty cycle corrector circuit 102 includes a differential amplifier circuit. The differential amplifier circuit may be configured to receive first and second external clock signals ECLK and ECLKB and generate first and second internal clock signals ICLK and ICLKB having a 50% duty cycle based on first and second average charge values dcc and dccb, respectively, provided by the duty cycle detector circuit 104. However, the analog duty cycle correction circuit may experience a time delay while the capacitors of the charge pumps are recharged after power is supplied to the integrated circuit memory device.
Time delay issues with respect to analog duty cycle correction circuits have been addressed by, for example, providing digital duty cycle correction circuits. Conventional digital duty cycle correction circuits may include an analog duty cycle correction circuit and/or a delay-locked loop (DLL) circuit.
Referring now to FIG. 5, a block diagram illustrating a digital duty cycle correction circuit 500 including an analog duty cycle correction circuit will be discussed. The digital duty cycle correction circuit 500 may convert first and second outputs dcc2 and dcc2b of a duty cycle detector circuit 504 into digital signals using an analog to digital converter 506 and may use a counter circuit 508 to save the results. The digital duty cycle correction circuit 500 converts the digital signals saved in the counter circuit 508 back to analog signals using the digital to analog converter 510, and provides the first and second outputs of the digital to analog converter 510 to the duty cycle corrector circuit 502 to correct the duty cycle of the first and second external clock signals ECLK and ECLKB.
The digital duty cycle correction circuit 500 saves the digitized information when power is removed from the integrated circuit memory device. Thus, when the power is resupplied to the integrated circuit memory device, the digital duty cycle correction circuit 500 can use the saved digital information by converting the information into analog signals using the digital to analog converter 510. The digital duty cycle correction circuit illustrated in FIG. 5 may include additional circuitry to implement the operations discussed above. Accordingly, the overall size of the integrated circuit may be increased. The increase in size may be a problem as the size of integrated circuit devices continue to decrease.
Referring now to FIG. 6, a block diagram illustrating a digital duty cycle correction circuit 600 including DLL circuits will be discussed. FIG. 7 is a timing diagram illustrating timing operations of the digital duty cycle correction circuit 600. As illustrated in FIG. 6, the digital duty cycle correction circuit includes first and second DLL circuits 602 and 604 for correcting duty cycles of first and second external clock signals ECLK and ECLKB. The first DLL circuit 602 generates a first clock signal CLK_R that is synchronized to a rising edge of an external clock signal ECLK and the second delay-locked loop circuit 604 generates a second clock CLK_F that is synchronized to a falling edge of the external clock signal ECLK. The second clock signal CLK_F is inverted using a first inverter U62 and becomes a third clock signal CLK_S. As illustrated, the digital duty cycle correction circuit 600 may also include second through fourth inverters U61, U63 and U64.
If the rising edges of the first and third clock signals CLK_R and CLK_S have a 50/50 duty cycle as illustrated in FIG. 7, an input clock signal ICLK having a 50/50 (A=B) duty cycle may be generated. A digital duty cycle correction circuit 600 including a DLL circuit may be smaller than a digital duty cycle correction circuit including an analog duty cycle correction circuit, but typically includes a DLL circuit because it uses a delay line of the DLL circuit.